Sunday, June 5, 2016

Progress on I/O processor for PI Zero/Orange PI

Made progress this week on I/O processor:

  1. PI zero CPU usage is down to 2% 
    1. Using DMA 64 byte packets 
    2. Sending two packets for one transaction 20us apart
      1. SPI rx/tx buffers are sent each clock, so, two transactions are needed., first transaction is CMD (Write/Read) elements the second is the response with the read data.  
  2. Updated I/O processor to use FreeRTOS v9.0.0.0
    1. Fixed interrupt priority issue causing lockup
    2. Adding I2C for LCD
    3. Need to test GPS serial 
    4. Adding PWM generation 
Here is a trace of a single transaction (CMD)/Response.  It takes .261ms to complete a CMD.  The I/O processor can process the command and re-trigger the DMA in less then 30us (Channel 04)

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