Tested FPGA based pwm encode/decode. Using Hobby King HK-16A V2 6 channel transmitter and decoding 6 channels of PWM from the receiver.. Encoding 4 PWM with a 1-2ms pulse width to 4 ESCs. The biggest issue generating PWM is to complete the last cycle before apply the next update.
Next step is to integrate into BetaFlight Linux Port, the goal is to be flying in a month.
All the code is on github.
Wednesday, January 8, 2020
Sunday, January 5, 2020
New logic analyzer
It was time to update to a better logic analyzer, LA2016. I have been using 8 channel original saleae. The LA2016 is a lot faster, 200Mhz and has internal storage with advance triggering.
One of the biggest issues I've been running into is tracing fast digital signals when developing FPGA code. CYC1000 uses Cyclone 10LP FPGA, have used Quartus internal logic analyzer a couple of times to trace/debug designs. But, I still like to have one around, so, the LA2016, so far it has been very handle, with a 1Mhz signal with a pulse width of 15ns was not an issue. But, also still getting up to speed on Verilog, have been working on test benches and verilator C++ test code. This way modeling and formal verification should cover most of the issues I've having debugging designs.
While debugging PWM state machine, the power supply driving my ESC tripped on overload. No, it does not power one, so, have another one on order, 12v 10amp. So, will be a little more careful.
Looks, like the PWM output should be working now, there was a glitch when setting a new PWM value, the duty cycle was going to 80% causing some ESC to stop.
One of the biggest issues I've been running into is tracing fast digital signals when developing FPGA code. CYC1000 uses Cyclone 10LP FPGA, have used Quartus internal logic analyzer a couple of times to trace/debug designs. But, I still like to have one around, so, the LA2016, so far it has been very handle, with a 1Mhz signal with a pulse width of 15ns was not an issue. But, also still getting up to speed on Verilog, have been working on test benches and verilator C++ test code. This way modeling and formal verification should cover most of the issues I've having debugging designs.
While debugging PWM state machine, the power supply driving my ESC tripped on overload. No, it does not power one, so, have another one on order, 12v 10amp. So, will be a little more careful.
Looks, like the PWM output should be working now, there was a glitch when setting a new PWM value, the duty cycle was going to 80% causing some ESC to stop.
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