Making progress on getting fast serial mode working on the CYC1000. The first step was to create some verilog code to route signals out to a header to validate the data using a saleae Logic Analyzer, also generate a clock.
Configured port B to opto-ioslate and keep the driver virtual serial port. This allows Linux to standard serial over USB but the FTDI converts the serial stream into fast serial using the mpsse.
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