Using FPGA to accelerate serial protocol handling adding two AXI Stream blocks.

 I have been working on communication protocol to the CMOD-S7 and CYC1000 via the FTDI over USB.  One of the issues is round-trip-time.  Currently the packet handling is done all by the MicroBlaze.  There are to basic packet handling duties the Microblaze performs in the RX/TX data path:

• Stripping or adding ESC formatting.  This loosely follows SLIP/PPP serial encoding.  
• Calculating CCITT CRC-16

 So, to lower the round trip time, I have been working on two independent AXI Stream blocks:

1. 16 bit CRC, will calculate the CRC per byte when TLAST is raised append the two bytes.
2. Packet format: add SOP (start of packet byte), ESC any bytes that are SOP,EOP, or ESC and add EOP when TLAST is raised. 

Using just the MicroBlaze, the ping rate is 1.7Mpbs, adding the two AXI stream pushes the rate to 2.7Mbps.

 

Here is a block diagram from vivado.

 The next goal is to eliminate the MicroBlaze processor and add a AXI switch.  The serial protocol has a ToPort, this will be used for the AXI Stream ID.  

This project take some time, the goal is to push the data rate to 12Mbps, maybe add the ADC and temperature sensor, to also push data via AXI stream.

Using AXI stream with DMA on a CMOD-S7 FPGA board

After a several weeks of tweaking, DMA driver and Verilog, AXI Stream serial TX/RX using DMA with the MicroBlaze soft core is working.

Over the past several months I have been using Fast Serial mode with FTDI, but it is only half duplex, if the PC and FPGA try to send messages at the same time, the FTDI chip does some weird things depending on the state if the FDSI and FSDO, worked with tech support, "should only be used with a half duplex protocol".  

So, back to standard serial, the FTDI serial interface can support 12Mbps in full duplex, so, it is possible to have the FPGA  and PC send async messages.  So, how to get 12 Mpbs to the Spartan 7?

Created a axis_serial RTL (In verilog) that can stream TX/RX bytes out to the FTDI chip at 12Mpbs.   This is a real simple block, used serial code from Nandland with a AXI stream wrapper. Also this wrapper looks at the incoming bytes from the serial and will raise TLAST for EOP (End of packet) byte.  TLAST is connected to the DMA block and this will terminate the DMA and the RX buffer is now filled with a packet.  

The DMA driver is packet based, i.e. like Ethernet LWIP example, but in this case it is using a serial stream. This way the microbalze is not processing serial interrupts per byte, but, interrupt per packet.  

Configured the clock to be 120Mhz, the current "ping rate" is 1.7Mpbs in one direction, or 3.4Mpbs full duplex.  I'm working on offloading the CRC and packet ESC packing to the FPGA.  CRC is done, Packing is taking some time.  This will be in the TX direction for now, so, the rate should increase to 3.4Mbps in TX direction.

All of the code is in gitub.

Using SERV RISCV soft processor on CYC1000 FPGA board

I've been working on using a FPGA for I/O acceleration for low cost ARM boards for a while.  The first pass was done using standard Avalon bus master over Fast Serial interface using the FTDI chip.  Fast serial can use up to 50Mhz clock, but it was scale back to around 20Mhz for debugging with my old logic analyzer.  

The goal is to use HighSpeed USB between a low end ARM SBC and off load tasks like:

• Decoding PWM RC transmitter
• DSHOT150
• APA102 LED bar
  

Recently, I moved to using fusesoc tool and the SERV RISV processor for offloading some of the verilog coding effort.  So, far the project SERV RISCV is running, fast serial wishbone interface has been debugged.  Next is to update the protocol.  The project is on github.  Soon to follow a HacksterIO article

Using the SERV processor is SMALL, and can use several in this design, will use one for the accelerometer control.

PWM input is working (Betaflight and CYC1000)

Made some good progress on integrating CYC1000 FPGA into betaflight running on Linux.  The CYC1000 is a FPGA performing PWM decode (from cheap RC transmitter), PWM encode (oneshot125 or DSHOT), APA102 led strip and on board LED.  Updated betaflight to send requests to CYC1000 to read PWM registers via libftdi1 over USB.

Here is a youtube video of betaflight showing PWM decode and IMU.

Using Fast Opto-Isolated Serial Interface Mode in the FT2232H with CYC1000 FPGA and libftdi1

After learning more about FPGA programming i.e verilog, nmigen, migen, and generating test benches finally got back on finishing the Avalon bus for the quad-copter.

The core gateware is Avalon bus with slave PWM (oneshot125), DSHOT150, slave LED APA102, slave on board LED, slave PWM decoder, and general timer.  The master is using Avalon bus master  bytes to packet interface over Fast Opt-Ioslated Serial interface.  One of the issues I was having was how to communicate from Linux to the CYC1000 board, could do standard serial, the top speed is 2Mbps, so, took the time and implemented Opt-Isolated serial interface at 25Mbps.  Reading more about the interface it is half duplex, but, it is still faster than serial.

So, use the standard FTDI driver with Linux with standard tty termios, but after trying to get 1ms round trip packet processing, the CPU usage was high and still slow.  I tried setting  setserial /dev/ttyUSB0 low_latency, that helped but still high CPU usage.

Next was trying libftdi1, with a latency timer of 0.  After a few few mod's to libftdi1, using a 100us timer to generate packets and uses 40% CPU usage.  Validated the data stream using LA2016 Logic Analyzer and the rrt is 180us.  So, not bad. Next is to move everything on to the orangePI plus2 H5.

First project on Hackster.io

Hacksterio hosted webinar "Mini but Mighty: Motor control Live Build with MiniZed"  also Avnet/Hacksterio/Xilinix created a design challenge.  After several days of work, entered with a project on Hacksterio.    Will find out on 2/18 on the results.

PWM encode/decode is working using a FPGA

Tested FPGA based pwm encode/decode.  Using Hobby King HK-16A V2 6 channel transmitter and decoding 6 channels of PWM from the receiver..  Encoding 4 PWM with a 1-2ms pulse width to 4 ESCs.  The biggest issue generating PWM is to complete the last cycle before apply the next update.  

Next step is to integrate into BetaFlight Linux Port, the goal is to be flying in a month.

All the code is on github.