I've been working on using a FPGA for I/O acceleration for low cost ARM boards for a while. The first pass was done using standard Avalon bus master over Fast Serial interface using the FTDI chip. Fast serial can use up to 50Mhz clock, but it was scale back to around 20Mhz for debugging with my old logic analyzer.
The goal is to use HighSpeed USB between a low end ARM SBC and off load tasks like:
- Decoding PWM RC transmitter
- DSHOT150
- APA102 LED bar
Recently, I moved to using fusesoc tool and the SERV RISV processor for offloading some of the verilog coding effort. So, far the project SERV RISCV is running, fast serial wishbone interface has been debugged. Next is to update the protocol. The project is on github. Soon to follow a HacksterIO article
Using the SERV processor is SMALL, and can use several in this design, will use one for the accelerometer control.
