Using FPGA to accelerate serial protocol handling adding two AXI Stream blocks.

 I have been working on communication protocol to the CMOD-S7 and CYC1000 via the FTDI over USB.  One of the issues is round-trip-time.  Currently the packet handling is done all by the MicroBlaze.  There are to basic packet handling duties the Microblaze performs in the RX/TX data path:

• Stripping or adding ESC formatting.  This loosely follows SLIP/PPP serial encoding.  
• Calculating CCITT CRC-16

 So, to lower the round trip time, I have been working on two independent AXI Stream blocks:

1. 16 bit CRC, will calculate the CRC per byte when TLAST is raised append the two bytes.
2. Packet format: add SOP (start of packet byte), ESC any bytes that are SOP,EOP, or ESC and add EOP when TLAST is raised. 

Using just the MicroBlaze, the ping rate is 1.7Mpbs, adding the two AXI stream pushes the rate to 2.7Mbps.

 

Here is a block diagram from vivado.

 The next goal is to eliminate the MicroBlaze processor and add a AXI switch.  The serial protocol has a ToPort, this will be used for the AXI Stream ID.  

This project take some time, the goal is to push the data rate to 12Mbps, maybe add the ADC and temperature sensor, to also push data via AXI stream.

Using AXI stream with DMA on a CMOD-S7 FPGA board

After a several weeks of tweaking, DMA driver and Verilog, AXI Stream serial TX/RX using DMA with the MicroBlaze soft core is working.

Over the past several months I have been using Fast Serial mode with FTDI, but it is only half duplex, if the PC and FPGA try to send messages at the same time, the FTDI chip does some weird things depending on the state if the FDSI and FSDO, worked with tech support, "should only be used with a half duplex protocol".  

So, back to standard serial, the FTDI serial interface can support 12Mbps in full duplex, so, it is possible to have the FPGA  and PC send async messages.  So, how to get 12 Mpbs to the Spartan 7?

Created a axis_serial RTL (In verilog) that can stream TX/RX bytes out to the FTDI chip at 12Mpbs.   This is a real simple block, used serial code from Nandland with a AXI stream wrapper. Also this wrapper looks at the incoming bytes from the serial and will raise TLAST for EOP (End of packet) byte.  TLAST is connected to the DMA block and this will terminate the DMA and the RX buffer is now filled with a packet.  

The DMA driver is packet based, i.e. like Ethernet LWIP example, but in this case it is using a serial stream. This way the microbalze is not processing serial interrupts per byte, but, interrupt per packet.  

Configured the clock to be 120Mhz, the current "ping rate" is 1.7Mpbs in one direction, or 3.4Mpbs full duplex.  I'm working on offloading the CRC and packet ESC packing to the FPGA.  CRC is done, Packing is taking some time.  This will be in the TX direction for now, so, the rate should increase to 3.4Mbps in TX direction.

All of the code is in gitub.