Using FPGA to accelerate serial protocol handling adding two AXI Stream blocks.

 I have been working on communication protocol to the CMOD-S7 and CYC1000 via the FTDI over USB.  One of the issues is round-trip-time.  Currently the packet handling is done all by the MicroBlaze.  There are to basic packet handling duties the Microblaze performs in the RX/TX data path:

• Stripping or adding ESC formatting.  This loosely follows SLIP/PPP serial encoding.  
• Calculating CCITT CRC-16

 So, to lower the round trip time, I have been working on two independent AXI Stream blocks:

1. 16 bit CRC, will calculate the CRC per byte when TLAST is raised append the two bytes.
2. Packet format: add SOP (start of packet byte), ESC any bytes that are SOP,EOP, or ESC and add EOP when TLAST is raised. 

Using just the MicroBlaze, the ping rate is 1.7Mpbs, adding the two AXI stream pushes the rate to 2.7Mbps.

 

Here is a block diagram from vivado.

 The next goal is to eliminate the MicroBlaze processor and add a AXI switch.  The serial protocol has a ToPort, this will be used for the AXI Stream ID.  

This project take some time, the goal is to push the data rate to 12Mbps, maybe add the ADC and temperature sensor, to also push data via AXI stream.